In this work we describe the network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC components built from detailed circuit simulation. It makes use of the architectural evaluator, which performs a detailed global interconnect analysis within the framework of industry-standard design tools. Using low density parity check decoding (LDPC) as a test vehicle, the NoC simulator is used in an NoC design study, and shows a method by which on-chip networks can be optimized. The foundation for architectural and transaction based modeling is set by a demonstration of the functional 3D NoC Test Chip, a 3-ary 3-cube on-chip interconnection network implemented in a 3-tier three dimensional integrated circuit (3DIC) technology. The chip, being among the first and only functional synthesized academic 3DIC's, not only demonstrates the feasibility of inter-tier signaling in a 3DIC, but has enabled power measurements that bring credibility to our power modeling methodology. We discuss a characterization methodology for parameterized NoC router components, so that we can quickly and easily estimate the power, performance, and area overhead for a wide range of NoC systems. While the completed models are provided so that they may be used for architectural evaluation independent from the remainder of our simulation framework, we describe the architecture of the NoC simulator. The simulator is used to study various LDPC and NoC parameters to help with high level design decision making. The results make a compelling case for the 2D and 3D torus networks and very shallow network memory buffers. We also introduce the concept and show the importance of processing element throttle. Using the simulator, a pareto optimal set of NoC configurations for our application is produced.