| dc.contributor |
Electrical Engineering |
|
| dc.contributor |
Grigsby, L. L. |
|
| dc.contributor |
Blackwell, William A. |
|
| dc.contributor |
Krauss, H. L. |
|
| dc.contributor |
Ebert, Harry K. Jr. |
|
| dc.contributor |
VanLandingham, Hugh F. |
|
| dc.creator |
Chalkley, Hatcher Edward |
|
| dc.date |
2014-03-14T21:11:16Z |
|
| dc.date |
2014-03-14T21:11:16Z |
|
| dc.date |
1968-08-13 |
|
| dc.date |
2010-05-20 |
|
| dc.date |
2010-05-20 |
|
| dc.date |
2010-05-20 |
|
| dc.date.accessioned |
2023-03-01T08:11:38Z |
|
| dc.date.available |
2023-03-01T08:11:38Z |
|
| dc.identifier |
etd-05202010-020013 |
|
| dc.identifier |
http://hdl.handle.net/10919/37848 |
|
| dc.identifier |
http://scholar.lib.vt.edu/theses/available/etd-05202010-020013/ |
|
| dc.identifier.uri |
http://localhost:8080/xmlui/handle/CUHPOERS/276775 |
|
| dc.description |
The false lock characteristics of a sampled-data phase lock loop containing a phase detector with a sawtooth characteristic are investigated.
The ideal processor of data operated on by such a phase detector nonlinearity is derived in open-loop form. A second system is proposed which is shown to approximate the operation of the ideal system with increasing accuracy for decreasing noise variance. The operation of the approximate system is interpreted in geometric terms. This geometric interpretation is used to place a lower bound on the probability of false lock of the ideal system.
A suboptimal system which uses feedback and a time-varying linear filter is analyzed. It was necessary to use a computer to perform the integration leading to the probability distribution of the error of this system.
The bound on the probability of false lock for the ideal system is compared with the probability of a similar error for the suboptimal system. It is concluded that this bound is a conservative one. |
|
| dc.description |
Ph. D. |
|
| dc.format |
72 leaves |
|
| dc.format |
BTD |
|
| dc.format |
application/pdf |
|
| dc.format |
application/pdf |
|
| dc.language |
en |
|
| dc.publisher |
Virginia Tech |
|
| dc.relation |
OCLC# 20737342 |
|
| dc.relation |
LD5655.V856_1968.C44.pdf |
|
| dc.rights |
In Copyright |
|
| dc.rights |
http://rightsstatements.org/vocab/InC/1.0/ |
|
| dc.subject |
LD5655.V856 1968.C44 |
|
| dc.subject |
Electronic circuits |
|
| dc.title |
False lock in sampled-data phase lock loops |
|
| dc.type |
Dissertation |
|
| dc.type |
Text |
|