| dc.contributor |
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
|
| dc.contributor |
Beckmann, Nathan Zachary |
|
| dc.contributor |
Tsai, Po-An |
|
| dc.contributor |
Sanchez, Daniel |
|
| dc.creator |
Beckmann, Nathan Zachary |
|
| dc.creator |
Tsai, Po-An |
|
| dc.creator |
Sanchez, Daniel |
|
| dc.date |
2015-02-26T13:37:58Z |
|
| dc.date |
2015-02-26T13:37:58Z |
|
| dc.date |
2015-02 |
|
| dc.date.accessioned |
2023-03-01T18:10:50Z |
|
| dc.date.available |
2023-03-01T18:10:50Z |
|
| dc.identifier |
http://hdl.handle.net/1721.1/95648 |
|
| dc.identifier |
Beckmann, Nathan, Po-An Tsai, and Daniel Sanchez. "Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling." 21st IEEE Symposium on High Performance Computer Architecture (February 2015). |
|
| dc.identifier |
https://orcid.org/0000-0002-2453-2904 |
|
| dc.identifier |
https://orcid.org/0000-0002-6057-9769 |
|
| dc.identifier |
https://orcid.org/0000-0003-4561-6450 |
|
| dc.identifier.uri |
http://localhost:8080/xmlui/handle/CUHPOERS/279052 |
|
| dc.description |
Cache hierarchies are increasingly non-uniform, so for systems to scale efficiently, data must be close to the threads that use it. Moreover, cache capacity is limited and contended among threads, introducing complex capacity/latency tradeoffs. Prior NUCA schemes have focused on managing data to reduce access latency, but have ignored thread placement; and applying prior NUMA thread placement schemes to NUCA is inefficient, as capacity, not bandwidth, is the main constraint. We present CDCS, a technique to jointly place threads and data in multicores with distributed shared caches. We develop novel monitoring hardware that enables fine-grained space allocation on large caches, and data movement support to allow frequent full-chip reconfigurations. On a 64-core system, CDCS outperforms an S-NUCA LLC by 46% on average (up to 76%) in weighted speedup and saves 36% of system energy. CDCS also outperforms state-of-the-art NUCA schemes under different thread scheduling policies. |
|
| dc.description |
National Science Foundation (U.S.) (Grant CCF-1318384) |
|
| dc.description |
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Jacobs Presidential Fellowship) |
|
| dc.description |
United States. Defense Advanced Research Projects Agency (PERFECT Contract HR0011-13-2-0005) |
|
| dc.format |
application/pdf |
|
| dc.language |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.relation |
http://darksilicon.org/hpca/?page_id=53 |
|
| dc.relation |
Proceedings of the 21st IEEE Symposium on High Performance Computer Architecture |
|
| dc.rights |
Creative Commons Attribution-Noncommercial-Share Alike |
|
| dc.rights |
http://creativecommons.org/licenses/by-nc-sa/4.0/ |
|
| dc.source |
MIT web domain |
|
| dc.title |
Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling |
|
| dc.type |
Article |
|
| dc.type |
http://purl.org/eprint/type/ConferencePaper |
|