| dc.contributor |
Electrical and Computer Engineering |
|
| dc.creator |
Judge, Lyndon |
|
| dc.creator |
Mane, Suvarna |
|
| dc.creator |
Schaumont, Patrick R. |
|
| dc.date |
2013-06-24T18:16:31Z |
|
| dc.date |
2013-06-24T18:16:31Z |
|
| dc.date |
2012-09-01 |
|
| dc.date.accessioned |
2023-03-01T18:54:15Z |
|
| dc.date.available |
2023-03-01T18:54:15Z |
|
| dc.identifier |
Lyndon Judge, Suvarna Mane, and Patrick Schaumont, “A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication,” International Journal of Reconfigurable Computing, vol. 2012, Article ID 439021, 14 pages, 2012. doi:10.1155/2012/439021 |
|
| dc.identifier |
http://hdl.handle.net/10919/23259 |
|
| dc.identifier |
https://doi.org/10.1155/2012/439021 |
|
| dc.identifier.uri |
http://localhost:8080/xmlui/handle/CUHPOERS/281811 |
|
| dc.description |
Elliptic curve cryptography (ECC) has become a popular public key cryptography standard. The security of ECC is due to the difficulty of solving the elliptic curve discrete logarithm problem (ECDLP). In this paper, we demonstrate a successful attack on ECC over prime field using the Pollard rho algorithm implemented on a hardware-software cointegrated platform. We propose a high-performance architecture for multiplication over prime field using specialized DSP blocks in the FPGA. We characterize this architecture by exploring the design space to determine the optimal integer basis for polynomial representation and we demonstrate an efficient mapping of this design to multiple standard prime field elliptic curves. We use the resulting modular multiplier to demonstrate low-latency multiplications for curves secp112r1 and P-192. We apply our modular multiplier to implement a complete attack on secp112r1 using a Nallatech FSB-Compute platform with Virtex-5 FPGA. The measured performance of the resulting design is 114 cycles per Pollard rho step at 100 MHz, which gives 878 K iterations per second per ECC core. We extend this design to a multicore ECDLP implementation that achieves 14.05 M iterations per second with 16 parallel point addition cores. |
|
| dc.description |
This research was supported in part by the National Science Foundation Grant no. 0644070. |
|
| dc.description |
The Virginia Tech Open Access Subvention Fund subsidized the article processing fees to make this article open access. |
|
| dc.description |
Published version |
|
| dc.format |
15 pages |
|
| dc.format |
application/pdf |
|
| dc.format |
application/pdf |
|
| dc.language |
en |
|
| dc.publisher |
Hindawi Publishing Corporation |
|
| dc.rights |
Creative Commons Attribution 3.0 Unported |
|
| dc.rights |
http://creativecommons.org/licenses/by/3.0/ |
|
| dc.rights |
Copyright © 2012 Lyndon Judge et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. |
|
| dc.subject |
Elliptic curve cryptography (ECC) |
|
| dc.subject |
Elliptic curve discrete logarithm problem (ECDLP) |
|
| dc.subject |
Prime field arithmetic |
|
| dc.title |
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication |
|
| dc.title |
International Journal of Reconfigurable Computing |
|
| dc.type |
Article - Refereed |
|
| dc.type |
Text |
|