| dc.description |
Digital-to-analog converters are an essential part of modern electronic systems which demand low-power consumption, high-speed performance, and exceptional linearity. They have a seemingly infinite number of applications, and as commercial integrated circuit processes continue to delve further into deep sub-micron territory, their utility, performance, and efficiency will only improve.
This thesis focuses on the design and implementation of a 12-bit, 500 MHz, current steering DAC in a 45nm SOI CMOS process. The DAC was designed using a fully-segmented, or ‘thermometer-coded’ topology, and will be fabricated in the aforesaid process. Ultimately, the DAC is destined for integration in a K-band stepped-frequency FMCW radar system, where it will act as an intermediary between a direct-digital-synthesis submodule and a phase locked loop submodule. – The DAC will convert the DDS produced discrete-time sinewave output, which has a low over-sampling ratio, to an analog continuous time waveform suitable for bandpass filtering. Bandpass filtering then provides time-smoothing to improve phase noise and spurious levels from the PLL.
To fully realize a workable DAC, several other sub-systems exist which contribute to its overall function. The design and implementation of these sub-systems – digital thermometer decoders, D-Flip-Flops, and individual current cells – will be described in detail. Trade-offs and challenges encountered throughout the ‘creation-story’ of this system are also discussed. |
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