| dc.contributor |
Fouts, Douglas J. |
|
| dc.contributor |
Electrical Engineering |
|
| dc.creator |
Van Dyk, Steven E. |
|
| dc.date |
June 1995 |
|
| dc.date |
2013-04-29T22:51:10Z |
|
| dc.date |
2013-04-29T22:51:10Z |
|
| dc.date |
1995-06 |
|
| dc.date.accessioned |
2022-05-19T03:07:30Z |
|
| dc.date.available |
2022-05-19T03:07:30Z |
|
| dc.identifier |
http://hdl.handle.net/10945/31502 |
|
| dc.identifier.uri |
http://localhost:8080/xmlui/handle/CUHPOERS/79523 |
|
| dc.description |
The use of gallium arsenide (GaAs) logic circuits in high performance computers and digital systems in space applications is desirable due to their high speed and immunity to total dose radiation. Several problem areas must be overcome for more widespread use. First, GaAs MESFETs with short gate lengths are susceptible to single event upsets (SEU) in a high radiation environment and second, GaAs circuits consume relatively large amounts of static power. To overcome the shortcomings of these areas, a new type of GaAs logic family called Pseudo-Complementary MESFET Logic (PC ML) was designed. This new type of GaAs logic consumes less power than current logic families and provides improved tolerances to SEUs. Experiments which estimated the charge required to generate SEUs in PCML circuits are described. The power consumption of a test circuit using PCML is analyzed and the data presented for a comparison against other GaAs logic families. Further refinements to PCML are discussed. |
|
| dc.description |
http://archive.org/details/singleeventupset1094531502 |
|
| dc.description |
NA |
|
| dc.description |
NA |
|
| dc.description |
U.S. Navy (U.S.N.) author. |
|
| dc.format |
61 p. |
|
| dc.format |
application/pdf |
|
| dc.language |
en_US |
|
| dc.publisher |
Monterey, California. Naval Postgraduate School |
|
| dc.rights |
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. |
|
| dc.title |
Single event upsets and noise margin enhancement of gallium arsenide Pseudo-Complimentary MESFET Logic |
|
| dc.type |
Thesis |
|